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| WEDNESDAY, June 9, 2004, 2:00 PM - 4:00 PM | Room: 6C | ||
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TOPIC AREA: NANOMETER ANALYSIS AND SIMULATION | ||
| SESSION 28 | |||
| Yield Estimation and Optimization | |||
| Chair: John Cohn - IBM Corp., Essex Junction, VT | |||
| Organizers: Michael Orshansky, Sudhakar Bobba | |||
| Process variability has been at the forefront of the design and EDA communities. The recent work on statistical static timing is an example of the response of the EDA community to this important area. This session is an indicator of the next wave of research in this area, one which will begin to apply these algorithms to estimate and optimize the timing yield of a design. | |||
 28.1 |
Parametric Yield Estimation Considering Leakage Variability |
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| Speaker(s): | Rajeev R. Rao - Univ. of Michigan, Ann Arbor, MI | ||
| Author(s): | Rajeev R. Rao - Univ. of Michigan, Ann Arbor, MI Anirudh Devgan - IBM Corp., Austin, TX David Blaauw - Univ. of Michigan, Ann Arbor, MI Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI | ||
| 28.2 | A Methodology to Improve Timing Yield in the Presence of Process Variations | ||
| Speaker(s): | Sreeja Raj - Univ. of Arizona, Tucson, AZ | ||
| Author(s): | Sreeja Raj - Univ. of Arizona, Tucson, AZ Sarma Vrudhula - Univ. of Arizona, Tucson, AZ Janet M. Wang - Univ. of Arizona, Tucson, AZ | ||
| 28.3 | Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology | ||
| Speaker(s): | Seung Hoon Choi - Intel Corp., Hillsboro, OR | ||
| Author(s): | Seung Hoon Choi - Intel Corp., Hillsboro, OR Bipul C. Paul - Purdue Univ., West Lafayette, IN Kaushik Roy - Purdue Univ., West Lafayette, IN | ||
| 28.4 | Statistical Timing Analysis Based on a Timing Yield Model | ||
| Speaker(s): | Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada | ||
| Author(s): | Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada Noel Menezes - Intel Corp., Hillsboro, OR | ||
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